/* SPDX-License-Identifier: BSD-3-Clause */
/*
 * Copyright 2023-2024 NXP
 */

#ifndef __DT_BINDINGS_CLOCK_S32R45_CLK_H
#define __DT_BINDINGS_CLOCK_S32R45_CLK_H

#include <dt-bindings/clock/s32gen1-clock.h>

#define S32R45_CLK_GMAC1_REF_DIV		S32GEN1_CC_CLK(54)
#define S32R45_CLK_GMAC1_EXT_TX			S32GEN1_CC_CLK(56)
#define S32R45_CLK_GMAC1_EXT_RX			S32GEN1_CC_CLK(57)
#define S32R45_CLK_GMAC1_RMII_REF		S32GEN1_CC_CLK(58)
#define S32R45_CLK_SERDES1_LANE0_TX		S32GEN1_CC_CLK(59)
#define S32R45_CLK_SERDES1_LANE0_CDR	S32GEN1_CC_CLK(60)
#define S32R45_CLK_ACCEL_PLL_PHI0		S32GEN1_CC_CLK(62)
#define S32R45_CLK_ARM_PLL_DFS4_2		S32GEN1_CC_CLK(63)

#define S32R45_CLK(N)			S32GEN1_PLAT_CLK(N)
#define S32R45_CLK_INDEX(N)		S32GEN1_PLAT_ARRAY_INDEX(N)

#define S32R45_CLK_MC_CGM2_MUX0		S32R45_CLK(0)
#define S32R45_CLK_ACCEL3		    S32R45_CLK(1)
#define S32R45_CLK_ACCEL3_DIV3		S32R45_CLK(2)
#define S32R45_CLK_MC_CGM2_MUX1		S32R45_CLK(3)
#define S32R45_CLK_ACCEL4		    S32R45_CLK(4)
#define S32R45_CLK_MC_CGM2_MUX2		S32R45_CLK(5)
#define S32R45_CLK_GMAC1_TX		    S32R45_CLK(6)
#define S32R45_CLK_MC_CGM2_MUX3		S32R45_CLK(7)
#define S32R45_CLK_MC_CGM2_MUX4		S32R45_CLK(8)
#define S32R45_CLK_GMAC1_RX		    S32R45_CLK(9)
#define S32R45_CLK_PER_DIV4			S32R45_CLK(10)

#define S32R45_CLK_MIPICSI2_0_CTL		S32R45_CLK(11)
#define S32R45_CLK_MIPICSI2_1_CTL		S32R45_CLK(12)
#define S32R45_CLK_MIPICSI2_2_CTL		S32R45_CLK(13)
#define S32R45_CLK_MIPICSI2_3_CTL		S32R45_CLK(14)

#define S32R45_CLK_CTE_PER				S32R45_CLK(15)
#define S32R45_CLK_CTE_XBAR_DIV3		S32R45_CLK(16)

#define S32R45_CLK_EIM_DSP				S32R45_CLK(17)
#define S32R45_CLK_BBE32EP_DSP			S32R45_CLK(18)

#define S32R45_CLK_LAX_0_MODULE			S32R45_CLK(19)
#define S32R45_CLK_LAX_1_MODULE			S32R45_CLK(20)

#endif
